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CY7C1020DV33
512K (32K x 16) Static RAM
Features
* Pin-and function-compatible with CY7C1020CV33 * High speed -- tAA = 10 ns * Low active power -- ICC = 60 mA @ 10 ns * Low CMOS standby power * * * * * -- ISB2 = 3 mA 2.0V Data retention Automatic power-down when deselected CMOS for optimum speed/power Independent control of upper and lower bits Available in Pb-free 44-pin 400-Mil wide Molded SOJ and 44-pin TSOP II packages Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020DV33 is available in Pb-free 44-pin 400-Mil wide Molded SOJ and 44-pin TSOP II packages.
Functional Description[1]
The CY7C1020DV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.
Logic Block Diagram
Pin Configuration[2]
SOJ/TSOP II Top View
DATA IN DRIVERS
A7 A6 A5 A4 A3 A2 A1 A0
32K x 16 RAM Array
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER
BHE WE CE OE BLE
NC A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A4 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
ROW DECODER
A8 A9 A10 A11
A12
A13
Notes 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com 2. NC pins are not connected on the die.
Cypress Semiconductor Corporation Document #: 38-05461 Rev. *D
A14
*
SENSE AMPS
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised November 8, 2006
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CY7C1020DV33
Selection Guide
-10 (Industrial) Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 60 3 -12 (Automotive)[3] 12 100 15 Unit ns mA mA
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[4] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[4] ....................................-0.5V to VCC + 0.5V DC Input Voltage[4] .................................-0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
Operating Range
Range Industrial Automotive Ambient Temperature -40C to +85C -40C to +125C VCC 3.3V 0.3V Speed 10 ns 12 ns
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[4] GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz ISB1 ISB2 Automatic CE Power-down Max. VCC, CE > VIH Current--TTL Inputs VIN > VIH or VIN < VIL, f = fMAX Automatic CE Power-down Max. VCC, CE > VCC - 0.3V, Current--CMOS Inputs VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 -10 (Industrial) Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 60 55 45 30 10 3 2.0 -0.3 -1 -1 Max. -12 (Automotive) Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 100 90 60 50 15 Max. Unit V V V V A A mA mA mA mA mA mA
Input Load Current Output Leakage Current VCC Operating Supply Current
Notes 3. Automotive Product Information is Preliminary. 4. VIL (min.) = -2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns.
Document #: 38-05461 Rev. *D
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CY7C1020DV33
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF
Thermal Resistance[5]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board SOJ 59.52 36.75 TSOP II 53.91 21.24 Unit C/W C/W
AC Test Loads and Waveforms[6]
3.0V 90% 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V
Rise Time: 1 V/ns
ALL INPUT PULSES 90% 10% 10%
Z = 50 OUTPUT
30 pF*
GND
(a)
(b)
Fall Time: 1 V/ns
High-Z characteristics: R 317 3.3V OUTPUT 5 pF R2 351
(c)
Notes 5. Tested initially and after any design or process changes that may affect these parameters. 6. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c).
Document #: 38-05461 Rev. *D
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CY7C1020DV33
Switching Characteristics Over the Operating Range [7]
Parameter Read Cycle tpower[8] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU[11] tPD[11] tDBE tLZBE tHZBE Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Cycle[12] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to WE LOW to Low-Z[9] High-Z[9, 10] 7 10 8 8 0 0 7 5 0 3 5 8 12 9 9 0 0 8 6 0 3 6 ns ns ns ns ns ns ns ns ns ns ns VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to OE HIGH to CE LOW to CE HIGH to Low-Z[9] High-Z[9, 10] Low-Z[9] High-Z[9, 10] 0 10 5 0 5 0 6 3 5 0 12 6 0 5 3 6 3 10 5 0 6 100 10 10 3 12 6 100 12 12 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -10 (Industrial) Min. Max. -12 (Automotive) Min. Max. Unit
CE LOW to Power-up CE HIGH to Power-down Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z
Byte Enable to End of Write
Notes 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed 9. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. This parameter is guaranteed by design and is not tested. 12. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
Document #: 38-05461 Rev. *D
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CY7C1020DV33
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR
[5]
Description VCC Data Retention Current
Conditions
Min. 2.0
Max.
Unit V
VCC = VDR = 2.0V, CE > VCC - 0.3V, Industrial VIN > VCC - 0.3V or VIN < 0.3V Automotive 0 tRC
3 15
mA mA ns ns
tCDR tR[13]
Chip Deselect to Data Retention Time Operation Recovery Time
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS tRC CE tACE OE tDOE BHE, BLE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% tHZCE tHZBE DATA VALID tPD 50% ICC ISB tHZOE
HIGH IMPEDANCE
Notes: 13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 14. Device is continuously selected. OE, CE, BHE and/or BLE = VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05461 Rev. *D
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CY7C1020DV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[17, 18]
tWC ADDRESS
tSA CE tAW
tSCE
tHA tPWE
WE tBW BHE, BLE tSD DATA I/O tHD
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
tSA BHE, BLE
tBW
tAW tPWE WE tSCE CE tSD DATA I/O tHD
tHA
Notes: 17. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05461 Rev. *D
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CY7C1020DV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC ADDRESS
tSCE CE tAW tSA WE tBW BHE, BLE tPWE
tHA
tHZWE DATA I/O
tSD
tHD
tLZWE
Truth Table
CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O0-I/O7 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z High-Z I/O8-I/O15 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z High-Z Power-down Read--All bits Read--Lower bits only Read--Upper bits only Write--All bits Write--Lower bits only Write--Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 12 Ordering Code CY7C1020DV33-10VXI CY7C1020DV33-10ZSXI CY7C1020DV33-12ZSXE Package Name 51-85082 51-85087 51-85087 Package Type 44-pin (400-Mil) Molded SOJ (Pb-free) 44-pin TSOP Type II (Pb-free) 44-pin TSOP Type II (Pb-free) Automotive Operating Range Industrial
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05461 Rev. *D
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CY7C1020DV33
Package Diagrams
Figure 1. 44-pin (400-Mil) Molded SOJ (51-85082)
51-85082-*B
Document #: 38-05461 Rev. *D
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CY7C1020DV33
Package Diagrams (continued)
Figure 2. 44-Pin Thin Small Outline Package Type II (51-85087)
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05461 Rev. *D
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1020DV33
Document History Page
Document Title: CY7C1020DV33, 512K (32K x 16) Static RAM Document Number: 38-05461 REV. ** *A *B ECN NO. 201560 233695 262950 Issue Date See ECN See ECN See ECN Orig. of Change SWI RKF RKF Description of Change Advance Information data sheet for C9 IPP DC parameters modified as per EROS (Spec # 01-02165) Pb-free Offering in Ordering Information Changed I/O1 - I/O16 to I/O0 - I/O15 Added Data Retention Characteristics table Added Tpower spec in Switching Characteristics table Added 44-SOJ package diagram Shaded Ordering Information Reduced Speed bins to -8 and -10 ns Converted from Preliminary to Final Removed Commercial operating range Removed 8 ns speed bin Added Automotive information Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #4
*C *D
307596 560995
See ECN See ECN
RKF VKN
Document #: 38-05461 Rev. *D
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